Journal of Engineering and Applied Sciences

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Compact Hardware Implementation of FPGA Based RC6 Block Cipher

Faez F. Shareef , Ashwaq Talib Hashim and Waleed F. Shareef
Page: 598-601 | Received 21 Sep 2022, Published online: 21 Sep 2022

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Abstract

This study presents the implementation of RC6 Block cipher that involve encryption and decryption on FPGA Virtex II device with highly compact architecture through reuse the same units for the identical operation in both algorithms. The proposed design also analyzes the cipher mathematical operation to fit it into FPGA available resources.

How to cite this article:

Faez F. Shareef , Ashwaq Talib Hashim and Waleed F. Shareef . Compact Hardware Implementation of FPGA Based RC6 Block Cipher.
DOI: https://doi.org/10.36478/jeasci.2008.598.601
URL: https://www.makhillpublications.co/view-article/1816-949x/jeasci.2008.598.601