TY  - JOUR
T1  - VLSI Implementation of Full Adder-Subtractor Design
AU - Ahmad, Nabihah AU - Kang, Lim Yoong 
JO  - Journal of Engineering and Applied Sciences
VL  - 12
IS  - 14
SP  - 3752
EP  - 3757
PY  - 2017
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2017.3752.3757
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2017.3752.3757
KW  - Full adder-subtractor
KW  -CMOS
KW  -pass transistor
KW  -low power
KW  -low area
AB  - Low power consumption and high performance in Very Large Scale Integration (VLSI) design are the major concerns in order to develop an efficient electronic devices. Addition is commonly used arithmetic operation in most electronic system which requires high performance and low power consumption of full adder circuit. This study aimed to design a low power and high performance full adder-subtractor by using Complementary Metal Oxide Semiconductor (CMOS) technology. Four design approaches of 4 bit Full Adder-Subtractor (FAS) static CMOS FAS with Pass Transistor Logic (PTL) XOR, static CMOS FAS with Transmission Gate (TG) XOR, PTL FAS and TG FAS circuit have been implemented in 90 nm CMOS technology using synopsys galaxy custom designer and compared in term of power consumption, power-delay product and area. PTL FAS able to reduce 27.7% of overall transistor count compared to both conventional static CMOS approach. For the 4 bit FAS design, PTL logic approach able to reduce 37.78% of area occupied and 27.78% of transistor count compared to static CMOS approaches. TG FAS has the lowest power consumption with 112.81 μW followed by PTL FAS with 133.34 μW, less than both conventional static CMOS approach. Results show that the PTL and TG approaches offer a low area and power consumption with a high performance of full adder-subtractor design.
ER  -