TY  - JOUR
T1  - A 31-Level Asymmetrical Cascaded H Bridge Multilevel Inverter
AU - Gowrishankar, J. AU - Belwinedward, J. 
JO  - Journal of Engineering and Applied Sciences
VL  - 13
IS  - 12
SP  - 4542
EP  - 4550
PY  - 2018
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2018.4542.4550
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2018.4542.4550
KW  - The 31 level multilevel inverter
KW  -modulation technique and PIC16F877A controller
KW  -semiconductor
KW  -distortion
KW  -output
KW  -voltage
AB  - This project commenced with a 31-level Asymmetrical Cascaded H-Bridge Multilevel Inverter
(ASCHBMLI). The topology is based on a cascaded connection of single stage sub multilevel converter unit
and full bridge cascaded H-bridge inverter. The input DC voltage source of V <sub>dc1</sub>-V <sub>dc4</sub>are planned in 
paired type of voltage of 15 V <sub>dc1</sub>, 30 V <sub>dc2</sub>, 60 V <sub>dc3</sub>and 120 V <sub>dc4</sub>individually. The output voltage levels are 
2*(1+2+4+8)+1 = 31) 31 level. The low frequency pulse width modulation technique is utilized for controlling
the power semiconductor switches in the ASCHBMLI. Total harmonic distortion is analyses and executed in
real time system using PIC16F877A microcontroller.
ER  -