TY  - JOUR
T1  - Wire-demotion for Static Timing Optimization in Advanced Technology Nodes
AU - Darmi, Mohammed AU - Cherif, Lekbir AU - Benallal, Jalal AU - Elgouri, Rachid AU - Hmina, Nabil 
JO  - Journal of Engineering and Applied Sciences
VL  - 14
IS  - 10
SP  - 3283
EP  - 3288
PY  - 2019
DA  - 2001/08/19
SN  - 1816-949x
DO  - jeasci.2019.3283.3288
UR  - https://makhillpublications.co/view-article.php?doi=jeasci.2019.3283.3288
KW  - Static timing analysis
KW  -optimization
KW  -global route
KW  -wire delay
KW  -worst and total hold slack
KW  -worst andtotal negative slack
KW  -back-end-of-line
KW  -self-aligned double patterning
KW  -circuit performance
KW  -performance power area
AB  - In Integrated Circuits (ICs) conception, the timing optimization techniques continually need enhancements. One way to avoid area increase during hold optimization is to optimize routing in order to bring down the Worst Hold and the Total Hold Slacks (WHS/THS) before regular Hold optimization. High performance, low power and small area (PPA) are the most customer requirements from new technology nodes.
This indicates that any new optimization technique should improve one or all of the aforementioned requirements. This study, consider the high resistance sensitivity to “Self-Aligned Double atterning” (SADP) process as an advantage and suggest a new timing optimization technique based on wire promotion. It consists on driving the EDA tool to use high resistive SADP layers for wires on hold timing paths. Which will free-up less resistive No-SADP layers for wires on setup timing paths. The target nets are issued by a statistical
approach that helps on getting the targets with the maximum benefit. Experience on multiple 7 nm-SADP designs shows 41% WHS and 37% THS improvement with 0% area increase, compared to baseline flow. As
a consequence, the worst negative and the total negative slacks (WHS/THS) are also well conserved and even improved up to 24 and 83%, respectively in some test-cases.
ER  -