TY  - JOUR
T1  - An Analog Low Power VLSI Implementation of Artificial Neural Network Architecture
AU - Arumugam, S. AU - Rajeswaran, N. 
JO  - Asian Journal of Information Technology
VL  - 15
IS  - 5
SP  - 955
EP  - 960
PY  - 2016
DA  - 2001/08/19
SN  - 1682-3915
DO  - ajit.2016.955.960
UR  - https://makhillpublications.co/view-article.php?doi=ajit.2016.955.960
KW  - low power
KW  -BPN
KW  -ANN
KW  -Analog VLSI
KW  -parallel computation
AB  - All the modern technologies in digital systems are slowly converting in to the analog implementation especially, for the fault tolerance and low power consumption. But, the analog implementation of parallel computation with ANN (Artificial Neural Network) in real time implementation is not an easy task in all aspects. This study mainly focuses on the implementation of Neural Network Architecture (NNA) with on chip learning in analog VLSI (Very Large Scale Integration). Back Propagation Neural network (BPN) algorithm is designed and simulated in analog domain by using tanner EDA tool.
ER  -