International Journal of Electrical and Power Engineering

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On Ways to Improve Adaptive Adjoint LMS Algorithm Using High Speed Architecture

N.J.R. Muniraj and R.S.D. Wahidhabanu
Page: 260-263 | Received 21 Sep 2022, Published online: 21 Sep 2022

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Abstract

This study proposes a technique termed Adjoint LMS which provides a simple alternative to the other adaptive algorithms. Here we implement Adjoint LMS algorithm into VLSI using Verilog HDL. This ASIC chip is designed, simulated and synthesized using Xilinx FPGA Virtex 2P(2vp30ff896-6) and the workability of the algorithm is tested for noise cancellation and verified using matlab.

How to cite this article:

N.J.R. Muniraj and R.S.D. Wahidhabanu . On Ways to Improve Adaptive Adjoint LMS Algorithm Using High Speed Architecture.
DOI: https://doi.org/10.36478/ijepe.2007.260.263
URL: https://www.makhillpublications.co/view-article/1990-7958/ijepe.2007.260.263