Journal of Engineering and Applied Sciences
ISSN: Online 1818-7803ISSN: Print 1816-949x
Abstract
Most of the Very Large Scale Integration (VLSI) applications such as digital signal processing, image processing, video processing and microcomputers extensively use arithmetic operations. The adder lies in the critical path of all the arithmetic operations so that it plays a crucial role in determining the overall system performance. Hence, low power dissipation, compact sized Integrated Circuit (IC) is highly required in modern digital applications. Recently, 10-Transistor Full Adder (10-T FA) becomes a good potential candidate for designing adder circuits because of reliable output and low power dissipation. This study presents the design and implementation of a low power 1-bit FA circuit. The design of the proposed full adder circuit is reducing power dissipation by optimizing the transistor size. The simulation results showed that the design required only 27x14.53 μm die area and dissipated as low as 0.1415 nW power. In comparison with previous studies, this proposed full adder demonstrates an advantage of low power dissipation and can be used at higher temperature with minimal power loss.
How to cite this article:
Azlia Binti Jaapar, Md. Mamun, Mohd. Marufuzzaman and Wan Mimi Diyana Wan Zaki. Design of a 10-T Low Power Full Adder for VLSI Applications.
DOI: https://doi.org/10.36478/jeasci.2013.15.20
URL: https://www.makhillpublications.co/view-article/1816-949x/jeasci.2013.15.20