Journal of Engineering and Applied Sciences
ISSN: Online 1818-7803ISSN: Print 1816-949x
Abstract
QR codes has gained more attention as an input interface to many embedded applications. However, some applications need extra computing resources which demandhigh-performance QR code decoder. This study suggests a hardware solution to accelerate the decoding function. The proposed design is implemented using CYCLON II FPGA from Altera with the decoded results display on a LCD. The initial experiments show that it is possible to decode the unmasked QR raw bits efficiently in real time which shows good potential to offload the computationally intensive task of QR image decoding process from the main processor and to room for advanced image pre-processing and security decryption algorithm to be implemented in FPGA.
How to cite this article:
Soon Nyeancheong, Wooi-Haw Tan, Muhammad Alhammami and Chee Pun Ooi. FPGA Hardware Implementation for Accelerating QR Decoding.
DOI: https://doi.org/10.36478/jeasci.2016.3273.3278
URL: https://www.makhillpublications.co/view-article/1816-949x/jeasci.2016.3273.3278