Journal of Engineering and Applied Sciences
ISSN: Online 1818-7803ISSN: Print 1816-949x
Abstract
Now a days multimedia applications are demanding high speed computing architectures. Adders and multipliers are very important functional blocks in Arithmetic and Logic Unit (ALU) of high speed computing architectures. For computing systems fast multiplication is always a significant requirement for high performance. This study presents the implementations of the high speed multipliers and their comparative analysis. In this study, we have proposed VLSI architecture for widely used parallel multipliers such as Booth’s multiplier, Wallace multiplier and Dadda tree multipliers in order to acquire their design attributes like speed, area. The acquired design parameters of the multipliers can be analyzed to design optimum speed Multiply and Accumulate (MAC) unit used for multimedia applications like filters, synthesizers, wireless communication channels, etc.
How to cite this article:
A.L. Siridhara, Mahendra Vucha and T. Ravinder. Performance Evaluation of Parallel Multipliers.
DOI: https://doi.org/10.36478/jeasci.2017.5186.5189
URL: https://www.makhillpublications.co/view-article/1816-949x/jeasci.2017.5186.5189