Journal of Engineering and Applied Sciences
ISSN: Online 1818-7803ISSN: Print 1816-949x
Abstract
Now a days chip designing has become more and more complex and then the transistor size had been decreased to nanometre level. The designing of the chip is taking so long and to test, it would take many more years. So, in order to decrease the testing time circuit is made to test itself making it possible to self test which is built inside the chip. Built in self test is design which can test itself and reduce the testing time. But, there are many more difficulties in continuing the processes. One among is the transition fault. Here, we present an idea to overcome the transition fault in the bist by using the fault generation of the transition pattern methods. They are LOC (Launch Off Capture) and LOS (launch off shift) methods. And also, we are implementing the enhanced launch off capture method in the bist. Work is done by the Xilinx 14.5 Version.
How to cite this article:
Meka Bharadwaj and Hari Kishore. Enhanced Launch-Off-Capture Testing Using BIST Designs.
DOI: https://doi.org/10.36478/jeasci.2017.636.643
URL: https://www.makhillpublications.co/view-article/1816-949x/jeasci.2017.636.643