Journal of Engineering and Applied Sciences
ISSN: Online 1818-7803ISSN: Print 1816-949x
Abstract
To represent complex number as single-unit binary number, a complex binary number utilizing base (-1+j) has been proposed in the scientific literature. In this study, we have designed a nibble-size adder based on this number system using the traditional truth table/Kmap approach and implemented it on Xilinx Virtex FPGAs. We have compared this design with the minimum-delay nibble-size complex binary adders and base-2 binary adders designed using decoder and ripple-carry principle. This research work leads us to the conclusion that the complex binary is a viable number system for designing Arithmetic and Logic Unit (ALU) of today’s microprocessors.
How to cite this article:
Tariq Jamil, H. Medhat Awadalla and Iftaquaruddin Mohammad. Design and Implementation of a Complex Binary Adder.
DOI: https://doi.org/10.36478/jeasci.2018.1813.1828
URL: https://www.makhillpublications.co/view-article/1816-949x/jeasci.2018.1813.1828