Journal of Engineering and Applied Sciences
ISSN: Online 1818-7803ISSN: Print 1816-949x
Abstract
Network-on-chip is one of the promising computing paradigms. Continuing research is carried out to improve the architecture and performance of networking techniques on the chip. In this research, we will demonstrate that routing efficiency can be improved in a mesh network using inbuilt "Agents" inside the processing elements. Moreover, this architecture is convenient to be used in either homogeneous or heterogeneous mesh networks. The packets are injected into various processing elements thorough multiple ports. The packet frame is designed and managed in such a way that keeping track of processed and un-processed objects is easy to track and helps maintain data integrity. We see that implementation results on FPGA show better area performance, minimized routing complexity and better throughput in a processing element.
How to cite this article:
Y.L. Ajay Kumar, D. Satyanarayana and D. Vishnu Vardhan. Routing Architecture for Efficient Network on Chip Using Agent.
DOI: https://doi.org/10.36478/jeasci.2018.6002.6007
URL: https://www.makhillpublications.co/view-article/1816-949x/jeasci.2018.6002.6007