Journal of Engineering and Applied Sciences
ISSN: Online 1818-7803ISSN: Print 1816-949x
Abstract
Power consumption and speed are two primary design constraints for Integrated Circuits (ICs). Improved performance on the basis of these is achieved primarily by reducing the silicon area of the IC. With reduced number of transistors to design a Full Adder (FA) circuit, high speed, low power Arithmetic Logic Units (ALUs) can be built which is a fundamental component of digital circuit. In this study, a performance analysis of a recently proposed 6-Transistor (6T) FA circuit has been presented using 32 nm Predictive Technology Models (PTM). Comparative analysis has been carried out between Low Power (LP) MOSFET and Double-Gate (DG) FinFET in the circuit. The PTM-LP MOSFET proved to be a better device for low power circuit while the DG FinFET proved a better alternative in terms of low chip area, high speed and good output voltage level and uniformity. Performance analysis also showed requirement of passive elements and transistor size modification for desired output with the 6T design.
How to cite this article:
S.M. Ishraqul Huq. Performance Analysis of 6-Transistor Full Adder Circuit using PTM 32 nm
Technology LP-MOSFETs and DG-FinFETs.
DOI: https://doi.org/10.36478/jeasci.2020.501.507
URL: https://www.makhillpublications.co/view-article/1816-949x/jeasci.2020.501.507